(China (Mainland))
Product Summary
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX?
architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Parametrics
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
Features
High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
■
Diagrams
Industrial temperature range
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
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 EPM3128ATC144-10 |
|
IC MAX 3000A CPLD 128 144-TQFP |
Data Sheet |
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EPM3128ATC144-10N |
|
IC MAX 3000A CPLD 128 144-TQFP |
Data Sheet |
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