Product Summary

EDD1216AJTA-5B-E Datasheet (PDF) - Elpida Memory - 128M bits DDR SDR

Parametrics

? Density:  128M bits 
? Organization 
?  2M words × 16 bits × 4 banks 
? Package:  66-pin plastic TSOP (II) 
?  Lead-free (RoHS compliant) 
? Power supply:  VDD, VDDQ = 2.5V ± 0.2V 
? Data rate:  400Mbps/333Mbps/266Mbps (max.) 
? Four internal banks for concurrent operation  
? Interface:  SSTL_2 
? Burst lengths (BL): 2, 4, 8 
? Burst type (BT): 
?  Sequential (2, 4, 8) 
?  Interleave (2, 4, 8) 
? /CAS Latency (CL): 2, 2.5, 3

Features

Features 
? Double-data-rate architecture; two data transfers per 
clock cycle  
? The high-speed data transfer is realized by the 2 bits 
prefetch pipelined architecture 
? Bi-directional data strobe (DQS) is transmitted 
/received with data for capturing data at the receiver  
? Data inputs, outputs, and DM are synchronized with 
DQS 
? DQS is edge-aligned with data for READs; centeraligned with data for WRITEs 
? Differential clock inputs (CK and /CK) 
? DLL aligns DQ and DQS transitions with CK 
transitions 
? Commands entered on each positive CK edge; data 
and data mask referenced to both edges of DQS 
? Data mask (DM) for write data 

Diagrams

EDD1216AJTA-5B-E Datasheet (PDF) - Elpida Memory - 128M bits DDR SDR